The present invention relates to an asynchronous transmission mode (ATM) cell switch system in a broadband ISDN, and specifically to an ATM switch circuit configuration system for switching an ATM cell after dividing it into a plurality of sub-cells or unit cells.
An ATM switch transmits fixed-length ATM cells, as of a fixed length, to an opposite state in cells at a high speed according to header information. Therefore, an appropriate ATM switch circuit configuration system is required for realizing an LSI system.
In an asynchronous transmission mode (ATM) system for a broadband ISDN transmission, the transmission speed of subscribers' lines is 155.52 Mbits/s or four times that speed, and data are transmitted after being divided into fixed length blocks called "an ATM cell". FIG. 1 shows an example of a configuration of an ATM cell. In FIG. 1, the length of an ATM cell 1 is a total of 53 bytes, 5 bytes of which are used as a header field, 2 indicating the cell's destination, and 48 bytes are used as an information field 3 for transmission data. The last 1 byte of the header field 2 stores header error control data and is used for header error control (HEC).
FIG. 2 shows an example of a configuration of a broadband ISDN system. In FIG. 2, digitized information of voice, data and images are divided into fixed length ATM cells having a header indicating a destination, etc., and then transmitted through a transmission circuit 6 by an ATM switch 5. On the receiving side, an ATM cell is switched by an ATM switch 7 and directed to a correspondent user terminal 8.
One conventional ATM circuit system is a multi-step gate type system. FIG. 3 shows a configuration of a single-input multi-step gate type system. In a multi-step gate type system, 1.times.2 unit switches are arranged orderly to allot one ATM cell. A unit switch in the first step works at the first bit data of the header field; a unit switch in the second step works at the second bit data of the header field; and a unit switch in the Nth step works at the Nth bit data of the header field. Thus, each unit switch automatically works according to the value of each header field to allot an ATM cell.
FIG. 4 shows an example of a configuration of a single input multi-step gate type system (N=3). In this example, an inputted ATM cell has a 3-bit header part. For example, if an ATM cell having a header 011 (the first three bits is inputted, 1.times.2 unit switches work after checking each it, thus outputting the ATM cell to an output terminal 4.
To allot a plurality of ATM cell inputs in a multi-step gate type system, 2.times.2 unit switches must be arranged in an orderly manner; a unit switch in the first step works at the first bit data of the header field; a unit switch in the second step works at the second bit data of the header field, and a unit switch in the Nth step works at the Nth bit data of the header field. Thus, each unit switch works automatically according to the value of each header field to allot ATM cells.
FIG. 5 shows a configuration of a multi-input multi-step gate type circuit.
FIG. 6 shows an example of a configuration of a multi-input multi-step gate type circuit. In this example, an inputted ATM cell has a 3-bit header part. For example, if an ATM cell having a header 011 (the first three bits) is inputted, 2.times.2 unit switches work after checking each bit, thus outputting the ATM cell to an output terminal 4. As shown in FIG. 6, a unit switch of each step is connected such that any ATM cell having the same header part can be outputted to the same output terminal even if it is inputted from different input lines.
In a multi-step gate type system in an ordinary ATM switch circuit system shown in FIGS. 3-6, cells having the same header data value is outputted to the same output terminal according to the wiring among 1.times.2 or 2.times.2 unit switches. As all headers except a header error control data are, for example, 32 bits long, the number of gate steps are 32; the number of basic unit switches of a single input multi-step gate type system is equal to the number of output lines-1; and the number of basic unit switches of a multiple input multi-step gate type system is equal to the number of input/output lines.times.32/2. Thus, the number of unit switches increases with the number of input/output lines. As the configuration is not in the hierarchical structure, the increase of input/output lines (a maximum of 2.sup.32) requires the addition of basic unit switches and extended modification of the connection among basic unit switches, thus making it very difficult to realize an LSI system.